1. Field of the Invention
The present invention relates to clock systems and, in particular, to an improved clock multiplexer.
2. Description of the Related Art
Many digital electronic devices require flexible clock management that allows switching between different clock sources and/or frequencies while the device remains operational. For example, power consumption can be optimized by using the maximum clock frequency only for processing of time critical tasks while a slower clock is applied to the system for other tasks. Typically, a clock multiplexer is employed to select between multiple clocks.
FIG. 1 illustrates such a clock multiplexer circuit. As shown in FIG. 1, a multiplexer 102 is provided which receives a CLK0 and a CLK1 input. The CLK0 input is output from a clock divider 104. A select signal SELECT is used to select between CLK0 and CLK1.
Any implementation of a clock multiplexer should guarantee that the duration of the multiplexed clock outputs remain intact (undistorted) and that the multiplexed clock is spike free. This is accomplished relatively easily if the select signal SELECT is synchronous to both source clocks. In FIG. 1, the two alternate clocks are synchronous to one another, so synchronizing the select signal is relatively straightforward. However, if the two alternate clocks are asynchronous to one another, a simple combinatorial multiplexer, as shown in FIG. 1, no longer generates a spike-free undistorted clock. But even in the case where both clocks are synchronous, the potential variations in the intrinsic and interconnect delays of the circuit components are much easier to deal with during physical implementation if no fixed relation is imposed on the arrival times of the clocks at the multiplexer.
Turning now to FIG. 2, a diagram of an exemplary known clock multiplexer is shown. The clock multiplexer 200 receives clock inputs CLK0 and CLK1, and a select input SELECT. The clock multiplexer 200 includes a pair of cross coupled clock gating elements 202a, 202b. As shown, each gating element 202a, 202b includes a flip flop 204a, 204b, an AND gate 208a, 208b and an inverter 206a, 206b. Clock inputs CLK0, CLK1 are provided to the inverters 206a, 206b, respectively. The flip flops 204a, 204b receive enable signals EN0 and EN1, respectively, and output enable signals CLK0_EN and CLK1_EN, respectively. By control of the enable signals CLK0_EN, CLK1_EN, the input clocks CLK0, CLK1 are either passed through the AND gates 208a, 208b, respectively, or the outputs of the AND gates GC0, GC1, are forced to 0. The clock gating elements 202a, 202b are coupled by way of AND gates 210, 212 and output OR gate 214. The AND gate 210 has two inverting inputs; the AND gate 212 has a single inverting input. On change of the select signal, the previously selected clock is disabled before the newly selected clock is enabled.
In particular, the SELECT signal is inverted at the input of the AND gate 210, but not the AND gate 212, such that SELECT will be clocked through only one or the other of the clock gating elements. Further, the output CLK1_EN of the flip flop 204b is fed back to the inverting input of the AND gate 210. The output CLK0_EN of the flip flop 204a is fed back to the inverting input of the AND gate 212. Thus, the enable signal EN0 is output from the AND gate 210 when the SELECT is low and the previous CLK1_EN is also low or inactive. Similarly, the enable EN1 is clocked through the flip flop 204b when the SELECT signal is high and the previous CLK0_EN is also inactive. A known variation of the circuit of FIG. 2 is to employ a pair of cascaded flip flops in each gating element.
While the circuit of FIG. 2 is generally effective in producing a clean switched clock, relative care must be taken to ensure that the select signal SELECT does not change without a clock being enabled and when both clocks have a falling edge near the same time. In such cases, one flip flop might latch the old value of select while the other is already latching the new value. This can result in both clocks being simultaneously enabled. For example, FIG. 3 is a timing diagram of the circuit of FIG. 2. Illustrated are the CLK0 waveform 350, CLK1 waveform 352, SELECT waveform 354, SELECT0 waveform 356, SELECT1 waveform 358, CLK0_EN waveform 360, CLK1_EN waveform 362, and CLK waveform 364. As shown, the CLK waveform 364 has a spike 301 when both clocks CLK0_EN and CLK1_EN are enabled.
These and other drawbacks in the prior art are overcome in large part by a system and method for clock multiplexing according to the present invention. According to one implementation, a pair of two-stage cross-coupled clock gating elements are controlled by a single asynchronous enable signal. On change of the enable signal, the previously selected clock always gets disabled before the newly selected clock is enabled.